A semiconductor manufacturing process involves the steps of exposing, etching, and thin-film deposition, which steps are repeated several or a dozen times. One critical factor in these steps is matching (overlay) of locations between a wiring pattern formed in an under layer and a wiring pattern to be formed in an upper layer in a plurality of wiring patterns stacked one on top of the other.
In a conventional approach, matching has been provided by making an alignment (an overlay inspection) by means of a light (an optical microscope and so on) in conjunction with a mark of a specified purpose (an overlay mark) employed for alignment of the locations between the pattern in the under layer and the pattern in the upper layer.